Brief Resume

Three-page CV can be found here (Last Update: April 2025).

Professional Experience

Description: Combining consistency and persistency models in datacenters, exploiting the sub-microsecond latency of RDMA, utilizing SmartNICs, and designing efficient distributed transactions. Additionally, working on fault tolerance for leaderless and CXL-enabled systems.

Graduate Research Intern (May 2024 - August 2024), Azure Research - Systems (Microsoft)

Description: Characterization and use case exploration for memory pooling with Compute Express Link (CXL).

Description: Evaluate and expand the in-house hardware prototypes designed and developed by the CARV laboratory. More specifically, provide a detailed performance analysis of the FPGA-based RDMA Engine, as well as optimize page-fault handling during RDMA.

Description: Provide support to handle dynamic page faults during RDMA transfers (MSc thesis).

Research topics (currently): Computer Architecture, Distributed Systems, CXL, Consistency, Persistency, NVM, and Distributed Transactions.
Advisor: Prof. Josep Torrellas
Graduate Student Member of the ACE Center for Evolvable Computing

M.Sc. Thesis: "Handling of Memory Page Faults during Virtual-Address RDMA"
- Objective: Aimed to avoid pinning of the page tables of processes, that would hinder the memory utilization. A non-pinned-memory-pages design results to page faults that require handling.
- Advisor: Prof. Manolis G.H. Katevenis
- Took place at CARV, ICS-FORTH [July 2017 - July 2019]
- Supported and used by the ExaNeSt project

B.Sc. Thesis: "IOMMU Support for Virtual-Address Remote DMA in an ARMv8 Environment"
- Objective: Effectively utilize ARM’s IOMMU (SMMU) on Xilinx Zynq Ultrascale+ in order to support virtual-addressed RDMA transfers. A mechanism was designed to enable seemless translation of virtual-to-physical addresses by utilizing the process page table.
- Advisor: Prof. Manolis G.H. Katevenis
- Took place at CARV, ICS-FORTH [June 2016 - Dec. 2016]
- Partly used by the ExaNeSt project