Brief Resume

Two-page CV can be found here (Last Update: December 2025).

Professional Experience

Research Assistant (Aug. 2020 - Present), i-acoma group and Siebel School of Computing and Data Science

Research on consistency and persistency models in datacenters, exploiting the sub-microsecond latency of RDMA, utilizing SmartNICs, and designing efficient distributed transactions. Focused on performance and fault tolerance for leaderless and Compute Express Link (CXL)-enabled systems.

Graduate Research Intern (May 2025 - August 2025), Microsoft's Systems Planning & Architecture (SPARC), within Azure Hardware Systems and Infrastructure (AHSI) organization.

Emerging CXL memory pooling and sharing devices; exploring functionality and performance.

Graduate Research Intern (May 2024 - August 2024), Azure Research - Systems (Microsoft)

Pre-silicon design and verification. Research on congestion control, fairness mechanisms, and formal analysis for CPU interconnects.

Profiling and expanding the in-house hardware prototypes designed and developed by the CARV laboratory. Detailed performance analysis of the FPGA-based RDMA Engine, as well as optimizing page-fault handling during RDMA.

PhD in Computer Science (2020 - Present), Siebel School of Computing and Data Science.

Research topics (currently): Computer Architecture, Distributed Systems, CXL, Consistency, Persistency, NVM, and Distributed Transactions.
Advisor: Prof. Josep Torrellas
Graduate Student Member of the ACE Center for Evolvable Computing

M.Sc. Thesis: "Handling of Memory Page Faults during Virtual-Address RDMA"
- Objective: Aimed to avoid pinning of the page tables of processes, that would hinder the memory utilization. A non-pinned-memory-pages design results to page faults that require handling.
- Advisor: Prof. Manolis G.H. Katevenis
- Took place at CARV, ICS-FORTH [July 2017 - July 2019]
- Part of the ExaNeSt project

B.Sc. Thesis: "IOMMU Support for Virtual-Address Remote DMA in an ARMv8 Environment"
- Objective: Effectively utilize ARM's IOMMU (SMMU) on Xilinx Zynq Ultrascale+ in order to support virtual-addressed RDMA transfers. A mechanism was designed to enable seemless translation of virtual-to-physical addresses by utilizing the process page table.
- Advisor: Prof. Manolis G.H. Katevenis
- Took place at CARV, ICS-FORTH [June 2016 - Dec. 2016]
- Part of the ExaNeSt project